Analog, mixed-signal and RF IC design services

Senior analog design capacity, from specification to silicon.

High-speed SerDes, DDR/LPDDR PHY, PLL and ADPLL, Bluetooth/BLE RF transceivers and UCIe die-to-die interfaces. Designed by engineers with 15+ years of production tape-outs each. Delivered through tape-out and silicon bring-up.

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Technical leads
15+ years each
Based in
Cairo, Egypt
Working overlap
EU full day · US morning · Asia afternoon
00.5 UI1 UI1.5 UI2 UI +V 0 −V NRZ · mask · sampling point
Illustrative NRZ eye diagram. Measured and simulated results for a specific block are shared under NDA.

Where our engineers have worked

Process nodes
[NODES: to be supplied, e.g. 28 nm, 22 nm FD-SOI, 16/12 nm FinFET, 7 nm, 5 nm]
Foundries
[FOUNDRIES: to be supplied, e.g. TSMC, Samsung Foundry, GlobalFoundries]
Tape-outs led by our engineers
[NUMBER: to be supplied]
EDA flows
[EDA TOOLS: licensed tools to be supplied, e.g. Cadence Virtuoso/Spectre, Synopsys PrimeSim, Siemens Calibre]

All work is under NDA. Node and foundry details for a specific block are shared after the NDA is signed.

Capabilities

Blocks we design and deliver

Five areas where our leads have taped out production silicon, plus the analog and mixed-signal blocks that surround them. Every figure below is a specification we substantiate with data under NDA.

High-speed SerDes

NRZ and PAM4 transceivers for PCIe, Ethernet, USB and JESD-class links.

  • NRZ and PAM4 to [DATA RATE: to be supplied] Gb/s per lane
  • TX FFE, RX CTLE + [NUMBER: to be supplied]-tap DFE, [CDR: baud-rate or oversampled] CDR
  • Protocols: [PROTOCOLS: to be supplied, e.g. PCIe 4.0/5.0, USB 3.2, 10/25G Ethernet, JESD204B/C]

DDR / LPDDR PHY

DDR4, DDR5, LPDDR4X and LPDDR5/5X PHYs: I/O, clocking, data paths, training and DFI.

  • DDR4/DDR5, LPDDR4X/LPDDR5(X) to [DATA RATE: to be supplied] Mb/s per pin
  • Write leveling, read gate, DQ/CA eye centering and Vref training
  • Per-bit deskew, ZQ calibration and ODT; DFI [VERSION: to be supplied]

PLL and ADPLL

Analog and all-digital PLLs for SoC clocking, SerDes references and RF synthesis.

  • Integer-N and fractional-N analog PLLs, [FREQUENCY RANGE: to be supplied] GHz
  • ADPLL (TDC + DCO) with integrated jitter [NUMBER: to be supplied] fs RMS
  • Reference spurs below [NUMBER: to be supplied] dBc; lock in [NUMBER: to be supplied] µs

Bluetooth / BLE RF transceivers

2.4 GHz Bluetooth Low Energy radios: LNA to PA, synthesizer and the analog modem path.

  • Bluetooth LE 5.x: LE 1M, LE 2M, LE Coded [SUPPORTED: to be confirmed]
  • RX sensitivity [NUMBER: to be supplied] dBm at [NUMBER: to be supplied] mA; TX [NUMBER: to be supplied] dBm
  • Integrated PA and LNA, fractional-N synthesizer with two-point modulation

UCIe die-to-die PHY

Universal Chiplet Interconnect Express PHYs for standard and advanced packaging.

  • UCIe [VERSION: to be supplied, e.g. 1.1 / 2.0], standard (2D) and advanced (2.5D) package
  • [NUMBER: to be supplied] GT/s per lane; x16 and x64 modules
  • Bump pitch [NUMBER: to be supplied] µm; [NUMBER: to be supplied] pJ/bit

Other analog and mixed-signal

Data converters, power management, clocking, sensor front-ends and full-custom layout.

  • ADC/DAC: [RESOLUTION: to be supplied] bit at [RATE: to be supplied] MS/s
  • LDO, DC-DC and bandgap: [SPECS: to be supplied]
  • Clocking, sensor front-ends and full-custom layout on your flow or ours

All capabilities →

How we work

Four steps. No surprises at tape-out.

The same process on every engagement, whether you take one block or a dedicated team.

  1. NDA and scoping

    A mutual NDA comes first. Then a scoping call with the engineers who will do the work, not a sales team. You receive a written scope, a resourcing plan and a risk list within [NUMBER: to be supplied] business days.

  2. Architecture and specification sign-off

    We write or review the block specification and run architecture-level models. Corners, supplies, interfaces, test modes and acceptance criteria are agreed in writing before the first schematic.

  3. Design and verification with weekly reviews

    Schematic, layout and verification proceed in your environment or in our isolated one. Every week you get a written status: milestones, open issues, corner results and risks. Reviews are held with your engineers, not about them.

  4. Tape-out and bring-up support

    We support DRC/LVS sign-off, final checks and the tape-out review. When first silicon returns, we work the bench plan, characterization and debug with you until the block meets its specification.

Why teams work with us

Senior people. Predictable delivery.

  • Engineers who have shipped silicon

    Our technical leads have each spent 15+ years designing and taping out production ICs. The people on the scoping call are the people who design your block.

  • Working hours that overlap with yours

    Full working-day overlap with Central and Eastern Europe; near-full with the UK. Four to five hours of overlap with the US East Coast each morning. Three to four hours of overlap with Japan, Korea, Taiwan and Singapore each afternoon.

  • Cairo cost structure, design-house review culture

    Senior rates are well below those of US and EU design houses. [NUMBER: indicative rate comparison to be supplied]. Rates and terms are scoped after NDA.

  • Strict IP protection

    NDA before any technical detail. Isolated per-client environments. Licensed EDA tools only. Nothing from one client is reused for another.

Engagement models

Four ways to add capacity

Dedicated design team

Named senior engineers embedded in your program, on your flow or ours, for six months or longer.

Fixed-scope block delivery

A defined block for a defined node, delivered to a signed-off specification with milestone acceptance.

IP porting and migration

Move an existing block or IP to a new process node, foundry or metal stack without losing a quarter.

Compare engagement models →

Case studies

Anonymized work, concrete numbers

Client names and product details stay confidential. Specifications, nodes and outcomes are listed where the client has approved them.

High-speed SerDes IP porting and migration

[CASE STUDY: anonymized, to be supplied] SerDes port to a new node

Challenge
[CHALLENGE: to be supplied. Suggested content: a proven transceiver on the old node had to ship on the new node; supply dropped from [VOLTAGE] to [VOLTAGE]; the metal stack changed; the original designers were on another program; the tape-out date was fixed by a customer commitment.]
Result
[RESULT: to be supplied. Suggested content: tape-out on the committed date; post-layout eye margin at the worst corner; silicon correlation results after bring-up; what the client did next.]
  • Data rate [NUMBER: to be supplied] Gb/s
  • Channel loss [NUMBER: to be supplied] dB
  • Energy [NUMBER: to be supplied] pJ/bit
  • Schedule [NUMBER: to be supplied] weeks

Node: [NODE: to be supplied] → [NODE: to be supplied]

DDR / LPDDR PHY Dedicated design team

[CASE STUDY: anonymized, to be supplied] Dedicated team on an LPDDR PHY

Challenge
[CHALLENGE: to be supplied. Suggested content: the client's PHY team lost headcount mid-program; training logic and the I/O cells were behind schedule; the SoC tape-out could not move.]
Result
[RESULT: to be supplied. Suggested content: PHY delivered to the SoC integration milestone; training convergence on first boards; margin measured on silicon; team extended to the next program.]
  • Data rate [NUMBER: to be supplied] Mb/s per pin
  • Team [NUMBER: to be supplied] engineers
  • Duration [NUMBER: to be supplied] months
  • Tape-outs [NUMBER: to be supplied]

Node: [NODE: to be supplied]

PLL and ADPLL Fixed-scope block delivery

[CASE STUDY: anonymized, to be supplied] Fixed-scope ADPLL for a SerDes reference

Challenge
[CHALLENGE: to be supplied. Suggested content: a start-up without an in-house clocking designer needed a low-jitter reference for its SerDes; the block had to port to a second node within a year; area was constrained by the die plan.]
Result
[RESULT: to be supplied. Suggested content: milestone acceptance on schedule; post-layout jitter and spur results at the worst corner; silicon measurements; port to the second node.]
  • Integrated jitter [NUMBER: to be supplied] fs RMS
  • Output [NUMBER: to be supplied] GHz
  • Power [NUMBER: to be supplied] mW
  • Area [NUMBER: to be supplied] mm²

Node: [NODE: to be supplied]

All case studies →

Security and IP protection

Your IP stays yours

Read our security practices →

  • Mutual NDA before any technical discussion.
  • Isolated design environment per client, with access limited to named engineers.
  • Licensed EDA tools only, on audited infrastructure.
  • No reuse of client IP, schematics, layouts or scripts across projects.
  • Export-control screening of every customer and engagement.
  • Data handed back and deleted at project end, with written confirmation.

Add senior analog capacity to your next tape-out.

Book a 30-minute NDA call with a technical lead. We reply within one business day.

Request an NDA call Engagement models