Capability

Analog and mixed-signal blocks

The blocks that surround a PHY or a radio: converters, regulators, references, oscillators and sensor front-ends, plus full-custom layout for designs your own team owns.

analog IC design servicesmixed-signal design servicesdata converter design

All figures are shared with supporting data under NDA.

Problems we solve

  1. Data converters

    SAR, pipelined and delta-sigma ADCs; current-steering and resistor-string DACs. [RESOLUTION: to be supplied] bit at [RATE: to be supplied] MS/s with [NUMBER: to be supplied] ENOB, including calibration where the architecture needs it.

  2. Power management

    LDOs with [NUMBER: to be supplied] dB PSRR at [FREQUENCY: to be supplied] and [NUMBER: to be supplied] mV dropout; DC-DC buck and boost converters; bandgap references at [NUMBER: to be supplied] ppm/°C; power-on reset and brown-out detectors.

  3. Clocking

    Crystal oscillators, RC and ring oscillators, DLLs, duty-cycle correction, clock distribution and glitch-free multiplexing.

  4. Sensor front-ends

    Chopper-stabilized and instrumentation amplifiers, capacitance-to-digital and temperature sensing, bias generation and low-leakage switching.

  5. Full-custom layout

    Matched and high-speed analog layout, RF layout with EM extraction, DRC/LVS/ERC sign-off and EM/IR analysis, on your flow and PDK or in our isolated environment.

Typical specifications we have delivered

All figures are shared with supporting data under NDA.

Process nodes

[NODES: process nodes delivered in this area, to be supplied]

Parameter Value
ADC [ARCHITECTURE: to be supplied] [RESOLUTION: to be supplied] bit, [RATE: to be supplied] MS/s, [NUMBER: to be supplied] ENOB
DAC [RESOLUTION: to be supplied] bit, [RATE: to be supplied] MS/s, [NUMBER: to be supplied] dB SFDR
LDO PSRR [NUMBER: to be supplied] dB at [FREQUENCY: to be supplied]; dropout [NUMBER: to be supplied] mV; [NUMBER: to be supplied] mA
DC-DC [TOPOLOGY: to be supplied]; [NUMBER: to be supplied] % peak efficiency; [FREQUENCY: to be supplied] MHz switching
Bandgap [NUMBER: to be supplied] ppm/°C; [NUMBER: to be supplied] % untrimmed accuracy
Oscillators [TYPES: to be supplied]; [NUMBER: to be supplied] ppm
Process nodes [NODES: process nodes delivered in this area, to be supplied]

What we deliver

  • Block specification and architecture note
  • Schematics, testbenches and corner setups
  • Layout GDS, DRC/LVS/ERC clean; LEF/LIB where applicable
  • Post-layout verification report across PVT, with Monte Carlo where mismatch matters
  • Behavioral models for top-level verification
  • Characterization plan and bring-up support

How we verify

  • Corner and Monte Carlo analysis of offset, gain and linearity
  • Stability and PSRR analysis of regulators across load and line
  • Transient and periodic-steady-state analysis of oscillators
  • Post-layout extraction with EM/IR analysis of supply routing

Discuss an analog or mixed-signal block

Send the specification, node and schedule. A lead will respond with questions and a scoping proposal.

Request an NDA call All capabilities