Capability

UCIe PHY design services

The physical layer of a chiplet link: transmitters, receivers, forwarded clocking, lane repair and sideband, for UCIe standard (2D) and advanced (2.5D) packaging. Designed with the bump map and the package in the loop from day one.

UCIe PHY designdie-to-die PHYchiplet interconnect design

All figures are shared with supporting data under NDA.

Problems we solve

  1. Data rate without equalization

    UCIe channels are short by design and meant to work with little or no equalization. We budget the driver, receiver and clock path for [NUMBER: to be supplied] GT/s at the specified BER in standard package, where loss and crosstalk are set by the substrate, not the die.

  2. Layout under the bump pitch

    At [NUMBER: to be supplied] µm bump pitch the PHY floorplan is set by the bump map. We co-design bump assignment, ESD and routing with your package team so the PHY fits and the shoreline bandwidth closes.

  3. Forwarded clocking and deskew

    Per-lane deskew, clock-to-data training and duty-cycle correction are specified with the package skew budget so the link trains reliably across corners and assembly variation.

  4. Lane repair and redundancy

    Redundant lanes and the repair multiplexer are part of the PHY, not an afterthought. We design the repair logic and assess the yield impact against your assembly data.

  5. Multi-module scaling

    Modules are tiled along the die edge. We plan clocking, supply and sideband for the number of modules your bandwidth target needs, and keep the per-module interface identical.

Typical specifications we have delivered

All figures are shared with supporting data under NDA.

Process nodes

[NODES: process nodes delivered in this area, to be supplied]

Parameter Value
Specification UCIe [VERSION: to be supplied]
Package Standard (2D) / Advanced (2.5D) [SUPPORTED: to be confirmed]
Data rate per lane [NUMBER: to be supplied] GT/s
Lanes per module x16 (standard) / x64 (advanced)
Bump pitch [NUMBER: to be supplied] µm
Energy efficiency [NUMBER: to be supplied] pJ/bit
PHY latency [NUMBER: to be supplied] ns
Sideband [NUMBER: to be supplied] Mb/s
Process nodes [NODES: process nodes delivered in this area, to be supplied]

What we deliver

  • PHY architecture, link budget and bump-map proposal
  • Analog front-end: TX drivers, receivers, forwarded clock path, PLL/DLL
  • Lane repair, deskew and training specification (RTL where in scope)
  • Sideband interface and power-management handshake
  • Package co-design inputs: bump map, ESD and routing constraints
  • Layout GDS and LEF/LIB; DRC/LVS clean
  • Verification and compliance test plan; interoperability plan
  • Bring-up and characterization support

How we verify

  • Channel simulation with package-extracted S-parameters and crosstalk
  • Timing-budget verification of the forwarded clock and deskew path
  • Lane repair and training sequence co-simulation with the AFE
  • Supply-noise and simultaneous-switching analysis across a full module
  • Post-layout extraction and corner analysis

Discuss a UCIe PHY

Send the package type, bump pitch, bandwidth target and node. A PHY lead will reply with a module plan and the first set of package questions.

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