UCIe in practice: what changes for your PHY team
A chiplet link is not a SerDes with a shorter channel. What a UCIe PHY team actually owns: bump maps, forwarded clocks, lane repair, sideband and the package.
Insights
Notes from the bench and the schematic
Short, specific articles on the problems we work on. Written by the engineers who do the work, for the engineers who will read it.
Latest
ADPLL vs analog PLL: choosing for your next node
A decision guide for choosing between an analog charge-pump PLL and an all-digital PLL: node, jitter target, spurs, area, portability and verification flow.
Porting a SerDes to a new node without losing a quarter
What changes when a transceiver moves between process nodes, where ports go wrong, and a plan that treats the port as a design project with a head start.
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