Capability

High-speed SerDes design services

Transmitter, receiver, clock and data recovery and clocking for serial links from [NUMBER: to be supplied] to [NUMBER: to be supplied] Gb/s per lane. We take a link from channel model and architecture through layout, extraction, compliance simulation and silicon correlation.

SerDes design serviceshigh-speed SerDesPAM4 transceiver design

All figures are shared with supporting data under NDA.

Problems we solve

  1. Closing the link budget on a lossy channel

    A channel with [NUMBER: to be supplied] dB of loss at Nyquist leaves little margin. We partition equalization between TX FFE, RX CTLE and DFE from a measured or modeled channel, then verify eye height and width against the protocol mask across PVT with statistical and time-domain simulation.

  2. Meeting the jitter budget at the worst corner

    TX random and deterministic jitter, PLL phase noise and CDR tracking bandwidth are budgeted together. The clock path is designed so the TX jitter specification holds at the slow-hot corner with supply noise applied, not only at typical.

  3. Compliance, not just function

    Transmitter eye, return loss, de-emphasis levels, receiver jitter tolerance and stressed-eye tests are simulated per the specification before tape-out. The compliance lab should confirm the design, not discover it.

  4. Power per bit

    For a target of [NUMBER: to be supplied] pJ/bit at [DATA RATE: to be supplied] Gb/s we trade slicer count, CTLE bandwidth, clocking architecture and supply domains against the channel. Margin is spent where the channel needs it, not everywhere.

  5. Porting a transceiver to a new node

    Moving a SerDes from [NODE: to be supplied] to [NODE: to be supplied] changes device models, the metal stack, ESD and supplies. We re-plan the clocking and ESD, re-simulate the budget and re-layout the critical paths rather than scaling the old layout.

Typical specifications we have delivered

All figures are shared with supporting data under NDA.

Process nodes

[NODES: process nodes delivered in this area, to be supplied]

Parameter Value
Data rate per lane [NUMBER: to be supplied] Gb/s
Modulation NRZ, PAM4
Channel loss supported [NUMBER: to be supplied] dB at Nyquist
Equalization TX [NUMBER: to be supplied]-tap FFE; RX CTLE + [NUMBER: to be supplied]-tap DFE
Clock recovery [CDR ARCHITECTURE: to be supplied, e.g. baud-rate phase-interpolator CDR]
TX random jitter [NUMBER: to be supplied] fs RMS
RX jitter tolerance Per [PROTOCOL: to be supplied] mask with [NUMBER: to be supplied] UI margin
Energy efficiency [NUMBER: to be supplied] pJ/bit
Lanes per macro [NUMBER: to be supplied]
Supplies [VOLTAGES: to be supplied] V
Process nodes [NODES: process nodes delivered in this area, to be supplied]

What we deliver

  • Architecture document with link budget, jitter budget and power estimate
  • Behavioral models: Verilog-A/AMS; IBIS-AMI models for channel simulation
  • Schematics with testbenches and corner setups
  • Layout GDS, DRC/LVS/antenna/density clean, with ESD and latch-up review
  • Post-layout extracted results across PVT corners
  • Verification report: eye diagrams, jitter decomposition, BER bathtub, return loss
  • Calibration and adaptation specification (RTL where in scope)
  • LEF/LIB, pin list, integration guide and package/PCB guidelines
  • Characterization and compliance test plan; bring-up support

How we verify

  • Statistical eye and BER analysis with the channel S-parameters
  • Transient simulation with supply noise and crosstalk aggressors
  • PSS/Pnoise and transient-noise jitter analysis of the clock path
  • Monte Carlo on slicers, CTLE and phase interpolators
  • Post-layout extraction (RC and inductance where relevant) at all corners

Discuss a SerDes block or port

Send the protocol, data rate, node and channel. A SerDes lead will come back with questions and a first view of the budget.

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