Capability

PLL and ADPLL design services

Integer-N and fractional-N analog PLLs, and all-digital PLLs built on a time-to-digital converter and a digitally controlled oscillator. Specified in integrated jitter, spurs, lock time and power, delivered with the phase-noise model and timing views your integration team needs.

PLL design servicesADPLL designall-digital PLL

All figures are shared with supporting data under NDA.

Problems we solve

  1. Sub-[NUMBER: to be supplied] fs jitter for a SerDes reference

    The integrated jitter budget is set by the VCO or DCO phase noise, the loop bandwidth and the reference. We optimize all three together and verify with transient-noise and PSS/Pnoise simulation at every corner.

  2. Fractional-N without the spurs

    Delta-sigma modulator order, dithering and phase-detector linearity are chosen together to keep fractional spurs below the target. Quantization-noise cancellation is applied where the specification needs it.

  3. Fast, deterministic lock

    Duty-cycled systems need lock in [NUMBER: to be supplied] µs. We design the acquisition aids, frequency calibration and loop-bandwidth switching so that lock time is deterministic, not statistical.

  4. ADPLL for portability and area

    An all-digital loop filter and a calibrated DCO port cleanly between nodes and shrink in advanced processes. We deliver the digital part as RTL and the analog part as layout with a clear, documented interface between them.

  5. Deterministic phase relationships

    Multiple PLLs that must stay phase-aligned, spread-spectrum clocking for EMI and glitch-free output switching are handled at the architecture level, not patched after layout.

Typical specifications we have delivered

All figures are shared with supporting data under NDA.

Process nodes

[NODES: process nodes delivered in this area, to be supplied]

Parameter Value
Architectures Integer-N, fractional-N (ΔΣ), ADPLL (TDC + DCO) [OTHERS: e.g. sub-sampling, to be confirmed]
Output frequency [RANGE: to be supplied] GHz
Reference frequency [RANGE: to be supplied] MHz
Integrated RMS jitter [NUMBER: to be supplied] fs ([INTEGRATION BAND: to be supplied, e.g. 12 kHz – 20 MHz])
Reference spur < [NUMBER: to be supplied] dBc
Fractional spurs < [NUMBER: to be supplied] dBc
Lock time < [NUMBER: to be supplied] µs
Power [NUMBER: to be supplied] mW at [FREQUENCY: to be supplied] GHz
Area [NUMBER: to be supplied] mm²
Spread spectrum [SSC: to be confirmed, e.g. down-spread 0.5 %]
Process nodes [NODES: process nodes delivered in this area, to be supplied]

What we deliver

  • Architecture document: loop design, noise budget and phase-noise model
  • Behavioral model (Verilog-A/AMS) with phase-noise and jitter prediction
  • Schematics, testbenches and corner setups
  • Layout GDS, DRC/LVS clean, with supply and substrate isolation review
  • ADPLL: digital loop filter and calibration RTL with verification
  • LEF/LIB and timing views; integration guide
  • Verification report: phase noise, jitter, spurs and lock time across PVT
  • Silicon correlation and characterization plan

How we verify

  • PSS/Pnoise phase-noise simulation of VCO/DCO, dividers and buffers
  • Transient-noise jitter simulation of the closed loop
  • Lock-time and stability analysis across loop-bandwidth settings
  • Spur analysis with supply ripple and substrate coupling
  • Mixed-signal co-simulation of ADPLL RTL with the analog DCO

Discuss a PLL or ADPLL

Send the output frequency range, reference, jitter and spur targets, and the node. A clocking lead will reply with an architecture proposal and a noise budget outline.

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