Capability

DDR and LPDDR PHY design services

The analog and mixed-signal side of a memory interface: I/O cells, DLL and PLL clocking, DQ/DQS and CA data paths, calibration and training, delivered with the DFI interface your controller expects.

DDR PHY designLPDDR5 PHY design servicesDDR5 PHY

All figures are shared with supporting data under NDA.

Problems we solve

  1. Timing closure at [DATA RATE: to be supplied] Mb/s per pin

    At high data rates the unit interval leaves [NUMBER: to be supplied] ps for everything. We budget DLL/PLL jitter, per-bit skew, duty-cycle distortion and ISI, then design the delay lines and deskew so the budget closes with margin at the slow corner.

  2. Training that converges on real boards

    Write leveling, read-gate training, read and write eye centering and Vref training are specified and verified against board-level SI models, so the sequence converges across the PVT, package and board variation you will ship.

  3. Impedance and termination

    Driver impedance, ODT and ZQ calibration are designed against the package and board stack-up, with return-loss and crosstalk analysis from a 3D-extracted model.

  4. Low-power states with fast exit

    Self-refresh, deep sleep and fast wake-up are built into the clocking and I/O from the start, with exit-latency budgets and retention of training results.

  5. Integration with your controller

    A clean DFI [VERSION: to be supplied] interface, LEF/LIB and timing models, and an integration guide that your SoC team can use without us in the room.

Typical specifications we have delivered

All figures are shared with supporting data under NDA.

Process nodes

[NODES: process nodes delivered in this area, to be supplied]

Parameter Value
Standards DDR4, DDR5, LPDDR4X, LPDDR5, LPDDR5X [SUPPORTED: to be confirmed per standard]
Data rate [NUMBER: to be supplied] Mb/s per pin
Channel width x16 / x32 / x64 [CONFIGURATIONS: to be supplied]
Training Write leveling, read gate, read/write eye centering, DQ and CA Vref
Calibration ZQ, ODT, per-bit deskew, duty-cycle correction
I/O supply [VOLTAGE: to be supplied] V
Controller interface DFI [VERSION: to be supplied]
Energy efficiency [NUMBER: to be supplied] pJ/bit
Process nodes [NODES: process nodes delivered in this area, to be supplied]

What we deliver

  • PHY architecture and timing budgets
  • I/O cells: drivers, receivers, ODT and ESD strategy
  • DLL/PLL, clock distribution and per-bit deskew
  • Training and calibration sequence specification (RTL where in scope)
  • Layout GDS, LEF/LIB and timing models; DRC/LVS clean
  • SI/PI analysis with package and board models
  • Verification report across PVT; DFI interface checks
  • Bring-up and margining plan for first silicon

How we verify

  • Timing budget verification with extracted delay lines across PVT
  • SI/PI co-simulation with package and board models
  • Training convergence simulation with skew and Vref variation
  • Duty-cycle and jitter analysis of the clock tree
  • Mixed-signal co-simulation of the training sequence with the PHY AFE

Discuss a DDR or LPDDR PHY

Tell us the standard, data rate, width, node and package. A PHY lead will respond with a resourcing plan and the questions we need answered first.

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