Capabilities

What we design

Five areas where our leads have taped out production silicon, and the analog and mixed-signal blocks around them. Each page lists the problems we solve, the specifications we have delivered and exactly what you receive.

Core expertise

High-speed SerDes

NRZ and PAM4 transceivers for PCIe, Ethernet, USB and JESD-class links.

  • NRZ and PAM4 to [DATA RATE: to be supplied] Gb/s per lane
  • TX FFE, RX CTLE + [NUMBER: to be supplied]-tap DFE, [CDR: baud-rate or oversampled] CDR
  • Protocols: [PROTOCOLS: to be supplied, e.g. PCIe 4.0/5.0, USB 3.2, 10/25G Ethernet, JESD204B/C]

DDR / LPDDR PHY

DDR4, DDR5, LPDDR4X and LPDDR5/5X PHYs: I/O, clocking, data paths, training and DFI.

  • DDR4/DDR5, LPDDR4X/LPDDR5(X) to [DATA RATE: to be supplied] Mb/s per pin
  • Write leveling, read gate, DQ/CA eye centering and Vref training
  • Per-bit deskew, ZQ calibration and ODT; DFI [VERSION: to be supplied]

PLL and ADPLL

Analog and all-digital PLLs for SoC clocking, SerDes references and RF synthesis.

  • Integer-N and fractional-N analog PLLs, [FREQUENCY RANGE: to be supplied] GHz
  • ADPLL (TDC + DCO) with integrated jitter [NUMBER: to be supplied] fs RMS
  • Reference spurs below [NUMBER: to be supplied] dBc; lock in [NUMBER: to be supplied] µs

Bluetooth / BLE RF transceivers

2.4 GHz Bluetooth Low Energy radios: LNA to PA, synthesizer and the analog modem path.

  • Bluetooth LE 5.x: LE 1M, LE 2M, LE Coded [SUPPORTED: to be confirmed]
  • RX sensitivity [NUMBER: to be supplied] dBm at [NUMBER: to be supplied] mA; TX [NUMBER: to be supplied] dBm
  • Integrated PA and LNA, fractional-N synthesizer with two-point modulation

UCIe die-to-die PHY

Universal Chiplet Interconnect Express PHYs for standard and advanced packaging.

  • UCIe [VERSION: to be supplied, e.g. 1.1 / 2.0], standard (2D) and advanced (2.5D) package
  • [NUMBER: to be supplied] GT/s per lane; x16 and x64 modules
  • Bump pitch [NUMBER: to be supplied] µm; [NUMBER: to be supplied] pJ/bit

Also in scope

Other analog and mixed-signal

Data converters, power management, clocking, sensor front-ends and full-custom layout.

  • ADC/DAC: [RESOLUTION: to be supplied] bit at [RATE: to be supplied] MS/s
  • LDO, DC-DC and bandgap: [SPECS: to be supplied]
  • Clocking, sensor front-ends and full-custom layout on your flow or ours

Common to every engagement

Specification first

No schematic starts before a written specification with corners, supplies, interfaces, test modes and acceptance criteria is signed off.

Verification you can audit

Every claim in the final report maps to a simulation setup you can re-run. Corner tables, not adjectives.

Tape-out and silicon

We stay through DRC/LVS sign-off, the tape-out review and silicon bring-up until the block meets its specification.

Not sure which page fits your block?

Describe the block in a sentence. We will tell you who on the team should be on the call.

Request an NDA call